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Instructors: Dr.-Ing. Wolfgang Heenes
Event type:
Integrated Course
Org-unit: Dept. 20 - Computer Science
Displayed in timetable as:
Einführung in CM
Subject:
Crediting for:
Hours per week:
3
Language of instruction:
German
Min. | Max. participants:
- | -
Course Contents:
Objectives:
Acquire Knowledge and Skills in
- modeling of hardware
- In modeling and design of finite machines and datapaths in respect of simulation and implementation in Verilog
- Logical synthesis and simulation
Course Content:
- Algorithmic state machine diagrams,
- FSM.models and level of abstraction. Communication mechanics for finite automatons, Verilog basic. Verilog models of finite automatons
- Logic synthesis and simulation
Diploma Supplement:
Computation structures, communication, state diagrams, Verilog, logic synthesis, simulation, high-level synthesis
Literature:
- Michael Ciletti, Advanced Digital Design with the Verilog HDL
- G. DeMicheli: Synthesis and Optimization of Digital Circuits, 1995
Preconditions:
Prerequisites: Technische Grundlagen der Informatik
Further Grading Information:
look https://moodle.informatik.tu-darmstadt.de/course/view.php?id=349
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