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Instructors: Prof. Dr. Hans Eveking
Event type:
Exercise
Org-unit: Dept. 18 - Electrical Engineering and Information Technology
Displayed in timetable as:
UE Verification Tech
Subject:
Crediting for:
Hours per week:
1
Language of instruction:
Englisch
Min. | Max. participants:
- | -
Course Contents:
Decision diagrams, Satisfiability checking, Symbolic state-space traversal, Reachability analysis, Semantics of temporal logics (CTL, LTL), Symbolic and bounded model-checking, Property specification languages (PSL, ITL)
Literature:
Th. Kropf: Introduction to formal hardware verification.
W.K. Lam: Hardware design verification.
Preconditions:
Basic knowledge of digital circuits
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