|
Instructors: Prof. Dr. Hans Eveking
Event type:
Lecture
Org-unit: Dept. 18 - Electrical Engineering and Information Technology
Displayed in timetable as:
VL Verification Tech
Subject:
Crediting for:
Hours per week:
3
Language of instruction:
Englisch
Min. | Max. participants:
- | -
Course Contents:
Decision diagrams, Satisfiability checking, Symbolic state-space traversal, Reachability analysis, Semantics of temporal logics (CTL, LTL), Symbolic and bounded model-checking, Property specification languages (PSL, ITL)
Literature:
Th. Kropf: Introduction to formal hardware verification.
W.K. Lam: Hardware design verification.
Preconditions:
Basic knowledge of digital circuits
Online Offerings:
moodle
|
