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Instructors: Prof. Dr.-Ing. Christian Hochberger
Event type:
Exercise
Org-unit: Dept. 18 - Electrical Engineering and Information Technology
Displayed in timetable as:
UE High-Level Synth.
Subject:
Crediting for:
Hours per week:
1
Language of instruction:
Englisch
Min. | Max. participants:
- | -
Course Contents:
- Mapping of behavioral descriptions (e.g. in the form of program fragments) on FPGA and CGRA structures
- Sub-tasks allocation, scheduling, binding
- Exact or heuristic solutions
- Design principles of heuristic solutions
Literature:
English slides can be obtained through Moodle.
Preconditions:
Knowledge of hardware synthesis on the basis of at least one hardware description lan-guage is required (e.g. Reese/Thornton: Introduction to Logic Synthesis Using Verilog Hdl oder Brown/Vranesic: Fundamentals of Digital Logic with VHDL Design). The student should have basic knowledge of at least one object oriented programming lan-guage, preferably Java
Online Offerings:
moodle
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