18-ho-2090-vl HDL: Verilog & VHDL

Instructors: Prof. Dr.-Ing. Klaus Hofmann; Ashok Kumar Jaiswal

Event type: Lecture

Org-unit: Dept. 18 - Electrical Engineering and Information Technology

Displayed in timetable as: HDL: Verilog & VHDL

Subject:

Crediting for:

Hours per week: 2

Language of instruction: Englisch

Min. | Max. participants: - | -

Course Contents:
Modelling of integrated circuits and systems using Verilog and VHDL on various levels of abstractions;

Literature:
Slide Copies

Preconditions:
At least one high-level Programming Language, Basic Know-How Linux/Unix, Computer Architectures