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Instructors: Prof. Dr.-Ing. Klaus Hofmann; Boris Traskov
Event type:
practical / lab /internship
Org-unit: Dept. 18 - Electrical Engineering and Information Technology
Displayed in timetable as:
HDL Lab
Subject:
Crediting for:
Hours per week:
3
Language of instruction:
Englisch
Min. | Max. participants:
- | 52
Course Contents:
Realisation of a VHDL- or Verilog-based VLSI System Design Project in a Team with industrial constraints
Literature:
Lecture slides „HDL: Verilog and VHDL“
Preconditions:
Lecture: HDL: Verilog and VHDL, at least one high-level Programming Language, Basic Know-How Linux/Unix, Computer Architectures
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