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Instructors: Ph.D. Martin Danek
Event type:
practical / lab /internship
Org-unit: Dept. 18 - Electrical Engineering and Information Technology
Displayed in timetable as:
A:PrakProcessorMicro
Subject:
Crediting for:
Hours per week:
2
Language of instruction:
Englisch
Min. | Max. participants:
- | -
Course Contents:
1. Set up the utgrlib VHDL sources in the home directory. Set up the utbinutils in the home directory. Compilation of introductory examples.
2.-3. Analysis of execution traces for introductory examples. Design of a FIR filter in micro-threaded assembly. Compilation, execution, analysis of pipeline efficiency.
4.-9. Re-design of existing blocks (choose from dcache, icache, regfile). Preparation of a TLM testbench. Coding and testing of the block in a stand-alone testbench.
10.-15. Integration of the block in UTLEON3, execution of micro-threaded programs, evaluation of performance analysis (% performance gain over the original block, % decreased resource requirements).
Literature:
A script is available as a published book and English slides can be obtained through moodle.
Preconditions:
Hands-on experience with at least one of Verilog or VHDL is expected. Basic understanding of FPGA technology and thorough knowledge of digital circuit design and computer architecture. Several tools used throughout the labs might require additional programming languages and tools (Perl, C, bash). This knowledge can be obtained during the labs.
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